83210-580-01 b isp2100a 1 features n available in two versions: r 66-mhz, 64-bit pci host bus interface r 33-mhz, 64-bit pci host bus interface n compliance with pci local bus speci?cation revision 2.1 n compliance with ansi scsi standard x3.131-1994 n supports all fibre channel topologies and classes of service n compliance with fibre channel arbitrated loop (fc-al) direct disk attach pro?le and fibre channel public loop (fc-pl) fabric loop attach pro?le , class 2 and class 3 service n compliance with pci bus power management interface speci?cation revision 1.0 (pc97) n supports 100 mbytes/sec sustained fibre channel data transfer rate n initiator or target mode n onboard risc processor to execute operations at the i/o control-block (iocb) level from the host memory n onboard gigabit serial transceivers n supports external transceivers with a 10-bit interface n supports pci dual-address cycle (64-bit addressing) and cache commands n no host intervention required to execute scsi operations from start to ?nish n simultaneous, multiple logical threads n full duplex frame buffer architecture n supports jtag boundary scan address figure 1. isp2100a block diagram receive frame buffer transmit pat h control registers pci interface frame buffer fibre engine register file alu isp2100a data pci address/data 64-bit, 66-mhz bus pci control external code/data memory flash bios receive data dma channel transmit data dma channel command dma channel mailbox registers control/ configuration registers boot code mem. i/f f i f o transmit frame buffer serial gigabit receiver 2 loop 10 ext. trans- ceiver in loop in 10 loop out serial gigabit transmitter receive pat h loop out 2 risc i/o bus nvram fibre channel qlogic corporation isp2100a intelligent fibre channel processors data sheet
2 isp2100a 83210-580-01 b qlogic corporation product description the isp2100a is a single-chip, highly integrated, bus master, fc-al processor that targets scsi applications. this chip connects the pci bus to a fibre channel loop and contains an onboard risc processor. the isp2100a is pin compatible with the isp2100. like the isp2100, the isp2100a is a fully autonomous device, capable of managing multiple i/o operations and associated data transfers from start to ?nish without host intervention. the isp2100a provides power management support in accordance with the pci bus power management interface speci?cation . the isp2100a block diagram is illustrated in ?gure 1. isp initiator and target firmware the isp2100a ?rmware implements a multitasking host adapter that provides the host system with complete scsi command and data transport capabilities, thus freeing the host system from the demands of the scsi fibre channel protocol (fcp). the ?rmware provides two interfaces to the host system: the command interface and the fibre channel transport interface. the single-threaded command interface facilitates debugging, con?guration, and recovering errors. the multithreaded transport interface maximizes use of the fibre channel and host buses. the isp2100a can switch between initiator and target modes. software drivers the isp2100a supports a host software interface similar to the isp1020/1040 family. existing 1020/1040 software drivers are easily modi?ed to support the isp2100a. bios ?rmware is available for the isp2100a. software drivers are available for the following operating systems: n aix n i 2 o n dos/windows n novell netware n os/2 n sco unix n unixware n windows 95; x86 and alpha systems n windows nt; x86 and alpha systems n solaris; x86 and sparc systems subsystem organization to maximize i/o throughput and improve host and loop utilization, the isp2100a incorporates a high-speed, proprietary risc processor; a fibre channel protocol manager (fpm); integrated frame buffer memory; and a host bus, three-channel, bus master dma controller. the fpm and host bus dma controller operate independently and concurrently under the control of the onboard risc processor for maximum system performance. the complete i/o subsystem solution using the isp2100a and associated supporting memory devices is shown in ?gure 2. interfaces the isp2100a interfaces consist of the fc-al interface, pci bus interface, risc interface, ?ash bios interface, and nvram control. pins that support these interfaces and other chip operations are shown in ?gure 3. response queue isp2100a figure 2. i/o subsystem design using the isp2100a pci interface fibre channel interface risc pci 64 loop in loop out 100 mbytes/sec fc_al private loop drive drive drive 16 host software driver request queue iocbs host memory p c i b u s external code/data memory
83210-580-01 b isp2100a 3 qlogic corporation fibre channel interface the isp2100a provides on-board gigabit transceivers for direct connection to the fibre channel loop on copper media. a standard 10-bit interface is also provided to connect to external transceivers, if desired. fibre channel protocol manager the isp2100a fpm supports the following: n support for one fibre channel loop n 100 mbytes/sec sustained data transfer rate n 10-bit interface to external transceivers n gigabit serial interface n integrated frame buffer that supports up to 2-kb frame payload the fpm includes an 8b/10b encoder and decoder, an elasticity buffer for clock skew management, and an fc-al state machine. the fpm transmits and receives at the full fibre channel rate of 106.25 mbytes/sec. the on-chip frame buffer includes separate areas for received data and transmit data, as well as areas for managing special frames such as command and response. the fpm receive figure 3. isp2100a functional signal grouping extint risc interface misc control rx9-0 lpenb fibre channel parallel interface isp2100a riscstb ecs3-2 raddr15-0 if frame pci bus interface st op ad63-0 trd y devsel perr idsel serr ird y r oe we rdata15-0 breq reset cbe7-0 par, par64 int a bclk nvdati nvcs nvdato nvclk nvram flash bios pdata7-0 bgnt clkout tstout ewrap lck_ref rdpar a ck64 req64 idenb tout9-0 rclk, rclk ri9-0 refclk2-1 gpio3-0 slsel txbvdd, txbvss iref fibre channel serial interface rx, rxp termres bgvdd, bgvss gdvss tx, txp rxbvdd, rxbvss rxvdd, rxvss txvdd, txvss vtxlo flashcs flashoe flashwr tdi test3-0 tms txclk tck exttrig ecs1-0 iocs power and ground vdd vdd4 vss m66en tdo trst
4 isp2100a 83210-580-01 b qlogic corporation path validates and routes frames received from the fibre channel to the appropriate area in the frame buffer. the transmit path transmits frames from the frame buffer to the fibre channel. the fpm automatically handles frame delimiters and frame control. pci interface the isp2100a pci interface supports the following: n 33-mhz or 66-mhz, 64-bit, intelligent bus master interface for fetching iocbs and data transfers n 64-bit host memory addressing (dual address cycle) n backward compatible to 32-bit pci n three-channel dma controller n 16-bit slave mode for communication with host n pipelined dma registers for ef?cient scatter/gather operations n 32-bit dma transfer counter for i/o transfer length of up to four gigabytes n support for pci cache commands n support for ?ash bios prom n support for subsystem id n 3.3v and 5.0v tolerant pci i/o buffers the isp2100a is designed to interface directly to the pci bus and operate as a 64-bit, dma bus master, which is backward compatible to 32-bit operation. this function is accomplished through a pci bus interface unit (pbiu) containing an onboard dma controller. the pbiu generates and samples pci control signals, generates host memory addresses, and facilitates the transfer of data between host memory and the onboard frame buffer. it also allows the host to access the isp2100a internal registers and communicate with the onboard risc processor. the isp2100a supports the minimum power management capabilities speci?ed in revision 1.0 of the pci bus power management interface speci?cation , which de?nes power states d0-d3, where d0 provides maximum power consumption and d3 provides minimal power consumption. the d1 and d2 power states provide intermediate power consumption. the d3 power state is entered by either software (d3 hot ) or by physically removing power (d3 cold ). hot and cold refer to the presence or absence of vcc, respectively. the isp2100a supports power states d0, d3 hot, and d3 cold. the isp2100a onboard dma controller consists of three independent dma channels that initiate transactions on the pci bus and transfer data between the host memory and frame buffer. the command dma channel is used mainly by the risc processor for small transfers, such as fetching commands from and writing status information to the host memory over the pci bus. the two data dma channels, one for transmit and one for receive, transfer data between the fc-al and the pci bus, allowing for fast context switching. the pbiu internally arbitrates between the two data dma channels and the command dma channel and alternately services them. each dma channel has a set of dma registers that are programmed for transfers by the risc processor. risc processor the isp2100a risc processor supports the following: n execution of multiple i/o control blocks from the host memory n reduced host intervention and interrupt overhead n one interrupt or less per i/o operation one of the major features of the isp2100a is its ability to handle complete i/o transactions from start to ?nish with no intervention from the host. this high level of integration is accomplished with an onboard risc processor. the isp2100a risc processor controls the chip interfaces; executes simultaneous, multiple iocbs; and maintains the required thread information for each transfer. packaging the isp2100a is available in a 256-pin ball grid array (bga) package. aix is a trademark of ibm corporation. alpha is a trademark of digital equipment corporation. dos, os/2, windows nt, and windows 95 are trademarks or registered trademarks of microsoft corp. novell and netware are registered trademarks of novell, inc. sco unix is a registered trademark of santa cruz operations. sparc is a trademark of sparc international, inc. unix is a trademark of at&t bell laboratories. all other brand and product names are trademarks or registered trademarks of their respective holders. ?march 11, 1998 qlogic corporation, 3545 harbor blvd., costa mesa, ca 92626, (800) on-chip-1 or (714) 438-2200 speci?cations are subject to change without notice. qlogic is a trademark of qlogic corporation.
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